Signal generator control circuit



June 21, ,1960 v. J. QuloGuE 2,942,237

sTCNAL GENERATOR CoNTRoL CIRCUIT Filed Jan, 30, 1959 C l. l

AGENT United stat-.slacht 1Q roughs Corporation Detroit Mich. a corporation of Michigan 9 r 9 n I Filed Jan. so, 1959, ser. No. 790,151 'lemma (cl. 34a-+149)v This yinvention relates to signal generator circuits, -and in particular to a signal generator circuit wherein an output signal which is produced inresponse to an inputv signal may be terminated early by a reject signal which has been derived from the input signal and which occurs within the enevelope of the said input signal. l Y Y The use of gating circuits and of gate signals provided thereby is well known in the electronic switching art. Such circuits provide important basic building blocks upon which the present day data processing systems operate. Often in dat-a processing operations, a particular gate signal is generated to provide an indication thata certain operation has taken place, and the system is made ready to perform the next operation in response to this indicative gate signal. For instance, the popular AND gate provides an output which indicates that the input channels to the AND gate `are all in a certain signal condition, either positive or negative, and that therefore another electronic operative step may take place -in response to the AND gate output signal. n

However, in some data processing operations, although a particular gate signal may be provided to indicate that certain operations have transpired, such gate signals may be considered cond-itional signals. In other words, the data processing system may be required to respond to such gate signals only if some second condition does not take place. For instance, a particular gate signal may indicate that the addition of two numbers has takenplace and that now the system is ready for a third number to be added. The requisite answer for the particular machine operation may at the Sametime dictate that the third number is not to be added lif the sum of the lrst two numbers is a negative sum. This is one illustration of a situation where the indicative gate signallwould be a -conditional signal. i l i l Normally, such a conditional operation .ishandled in 2,942,237 Patented June 21, 1960 ice . ond method wherein an additional step i`s provided to one of two ways. The first way, considering the above illustration, would be to initially examine the signof the sum, cr in the general case, interrogate `for a possible limitation which would render the gate signal non-controlling, Iand if such limitation is present, then-thegate signal would be prevented from being generated or transmitted. The second way would be to allow the gate signal to indicate that the machine is ready for the nextoperation, .but if the limiting condition hasvoccurred, to provide an additional operation to generate a second signal which would indicate to the system that the gate signal was an invalid signal and thereafter either prevent the subsequent operation or restore the system to its prior state.

The two described" methods for invalidating a particular indicative gate signal each require an inherent consumption of time. This is lapparent since a certain amount of time would be consumed to first examine the sign of a sum before deciding 'whether or notthe indicative gate signal should be advanced; and likewisela ceramount of time would be consumed under the secgenerate ausecond signal toindicate to the machine that the indicative gate' signal should be ignored and/or the information status restored. In high speed operations, such examination or reject time may not be readily available If there is a possibility of numerous reject occasions,fthe amount of overall examination and reject time becomes a great time burden on the system. For example, in a character recognition system wherein documents are passing through the system at the rate of four hundred inches per second, and the printed characters thereon are being read, there is very little time available for the system to make a decision as to whether or not there has been a proper reading of the characters, upon which decision the system must either accept or reject the document.

In one form of such character recognition systems, at the sampling or readout time, there is provided a gate signal which indicates to the system that the printed character has been translated into an electrical waveform signal and is ready to be recognized. The system as related to any single `read station should recognize only one character at a time, representing respectively the single characters of the document as they appear at the read station.

The system should not .indicate a valid recognition of a single character if in point of fact the system has spawned two or more signals which would indicate that the reading station has read two or more characters at the same time. Therefore, if two or more character waveform signals have been provided, it behooves the system, at the time of the sampling signal, to provide a reject signal to indicate to the system that although it is time to recognize the character in the reading sation, there have been two or more signals (atleast one spurious) provided and therefore the character on the document at the reading station must be rejected or regarded as a character not recognized. With the provision of such a reject control arrangement, character recognition systems can then provide an opportunity for the operator to examine the document, if -it should be desirable.

IIt is' therefore an aboject of the present invention to provide an improved control circuit for a gate signal generator device. f

IIt is a further object of the present invention` to provide a'control circuitfwhich can terminate an output signal, which is generated in response to an input signal, by a reject signal which is derived from the input signal and which occurswithin the envelope of the input signal.

In accordance with a main feature of the present rin- .vention there is provided an electron storage device which has a rst discharge path and a predetermined discharge time which primarily determines the duration of an output signal. Coupled to the electron storage device is a controllable secondV discharge path which, when conditioned, instantaneously and initially cuts 01T the output signal by a voltage shift and simultaneously substantially short circuits the electron storage device, thereby giving rise to a rapid discharge thereof, and consequently continuing the cut olf operation of the output signal which otherwise would have had a predetermined time `duration. .y

In accordance with another feature of the present -invention Athere isv provided, in conjunction with the above mentioned feature, an electron transfer device which is coupled between the electron storage device and a source of input pulses. -This arrangement causes the electron storage device to discharge when said electron transfer device conducts in response to an input pulse being applied. "I'he output pulse which is provided by the discharge of the electron storage device is thereby responsive to'aninputpulse.

In accordance with another feature of the present inl In accordance with still another feature of the present invention, there is provided abistablekv device which is coupled to the output signal and to the reject input signal to` provide, if the output signal occurs without any early termination thereof, that theV bistabley device will be transferred to a state representing a normal output, and on theY other hand,'if the reject signal occurs soy as to terminate the output signal early, that the bistable device will be transferredV to asecond condition indica-ting that there has been a rejectv of the outputsignal.

The foregoing and other objects and features' of this invention will be best understood by reference tothe' following description of a preferred embodiment of the invention taken in conjunction with the accompanying drawings, wherein:

Fig. 1 is a schematic and block diagram showing the inventive circuit of the present application coupledV to a portion of a character recognition system; and

Fig. 2 are waveforms to show the time relationship of the signals as they appear in the system.

In the character recognition system with which the present inventive circuit has been primarily employed', each Waveform signal lderived by scanning a printed character at the reading station is applied to and matched against a plurality of networks, each one of which represents a possible character to be read and each of which provides a maximum signal output, when compared to the output of the other networks, if the waveform signal to which the particular network is assigned is actually being `transmitted from the read station. It has been found that sampling a waveform signal over a predetermined time interval which cornmences just prior toa complete translation of a printed character into an electrical waveform up to and including such complete translation is more reliable than sampling the waveform Signal at theinstant that there is an apparent complete translation. For a number of reasons such as skew of the printed character relative to the head during docusignal or simultaneously at generation is over-ridden by aV reject pulse. If, during this coarse sampling time, two or more output signals are substantially equally large, so that either or any one might be considered maximum if it had appeared alone, a reject signal is generated with such reject signal being derived from the fine sampling time pulse and enveloped thereby.

AS, ,sussestsdsbovc and as will be explained .more fully lier'einafter, the inventive circuitr 4of the present application provides Ythat this reject signal, 'although en-n velopelflby thetinefsampling. time signal, cau'render the primary mission of the line sampling time signal ineiecl tive. Once` ,a rejectsignalvcondition is effected, this condition will 'remain until the next-tine' sampling time pulse. The initial missionjof the ,tine samplingtime pulse is to Wipe out any prior reject condition even though almost simultaneously a new reject pulse may beA generated to terminate the ne sampling, time pulse, again leaving a reject"l condition.' overlapping insures thateach time a' flue* sampling time pulse occurs, the system is instantaneously restored tofa non-reject condition so that if a no reject condition'is sensed, a valid recognition will be etfected inthe system.

An over-all consideration of the present inventivecircuit, as employed in this last-described character recognition system, reveals that a correlation network maximum output signal occurring within the coarse sampling time pulse, which has not been wiped out by a subsequen'tly larger vmaximum output, or has not been overridden by a reject pulse, will provide a valid recognition lstatus fora particula-r'character in the read station. In response to sucha valid recognition there may result an operation which,'for instance, might be the placing of thedocument (after a predetermined transport) into a particular" pocket of the sorting machine. On the other hand, if a`reject signal is provided and no subsequent rr'iaxirnumA output signal wipesout the reject indication, the character 4will be considered as not properly identified and, `in the sorter machine ill-ustration, the document will be placed inthe reject pocket.

Referring to Fig. l', there is' shown at 1l a read circuit arrangementy for a character recognition system which is Y symbolicof the type of .character recognition system dement transport, noise generated at the interruption of provides a maximum output signal, when compared with y the `other networks, should beby definition the time -for l sampling. If the signal is'sampledV over an interval, it has been found empirically and.v statistically that the ultimate maximum signalof a particular correlation network, when compared to the other networks, duringl the prea determined time interval .mosttruly indicates that actual character being read. j

The character recognition Asystem in connection `with which the present invention is described, employs a scheme of coarse time sampling the waveform signal vover a period of time from just prior to a complete trans'- lation up to and including the time of the complete translation. During this coarse sampling time, every maximum output signal generates a fine sampling time pulse which is recognized and remembered until either wiped i'.

scribed in a paperentitled Automatic Input for Business Data Processing Systems, by Eldredge et al., publilshedfintheV Proceedings of'the'Eastern Vi'oint Computer Conference, December -l956. In this type of character recognition system,'a printedv numeral or alphabetic letter 'passing the reading station is eitherl scanned by photosensitive means, or, having been printed Vwith magnetizable ink, isy read by` a Vmagnetic head. A dynamic signal having a characteristic waveform which makes the numeralvor other character identiliablel is` produced -at. the reading stationl by: virtues-of theser last-mentioned means. The Waveform signal Vproduced at the read station in the vsystem is passed along and applied, for comparison purposesQto a plurality of resistor networks which respectively representl the'ideal waveform of each of the 'characters which-may be read. Anideal waveform resistor network is provided for each of the possible characters to be read, and the individual network which provides' the maXimumsign'al output will be indicative of theparticular' character which hasl just passed under the fascination: 1

In Fi'gjl; the vechnnels 12 represent the outputs y from tive suchhetworks. i In actual practice, there will helas many channels asthere arenetworks, and as many networks as Vthere are different characters to be read..

Occasionally, in Such character recognition systems,lmore thanone network ,will provide a substantially equally large amplitude. signal, each of which, if standing alone, would be a rnaxin'nlm.`- This condition. must bevrecogni`z`ed. Since .'one, and only one, character or symbol shoul'dbe under ,thereading headY at any one reading, time,

tem described above, generator 14 would provide a coarse and fine timing gate pulse as described above, and in the description to follow the gate pulse 18 is considered to be the fine timing pulse. The sampling signal generator 14 passes a gating signal to the comparison gate and reject signal generator 13, as well as to the transistor 15. At thecomparison gate 13, if one, and only one, of the channels 12 has a signal thereon there is no reject pulse provided on the channel 16; however, if more than one of the channels 12 has a signal thereon then there will be a reject signal such as the signal 17 provided on the channel 16.

Considering more directly the role of the present inventive circuit, assume that neither the sampling pulse 18 nor the reject pulse 17 has been applied. Without either of the pulses 17 or 18 being applied, the circuit is in a quiescent state and the transistor 19 is conducting due to thev negative bias on its base provided by source 22 by way of resistor 21. There will be base current ow from the ground reference potential at 20 through the emitterbase junction of transistor 19, through the resistor 21 to the source of negative reference potential 22. At the same time the base current will be charging the condensor 23, through the resistor 24, to the negative potential at 22. The condensor 23 will be charged in accordance with the polarities shown thereon, giving rise to an approximate 6vvolt dilerence thereacross when the condensor is fully charged. Point 25 will remain sufticiently negative to keep the transistor 19 conducting, therefore the condensor 23 develops a potential thereacross which is slightly less than 6 volts. Since the approximate 6 volt dilerence is measured `from the -6 volt potential level, they point 25 is slightly negative to ground potential, as explained above. There will alsobe collector current ilowing through the transistor 19 and through the resistor 26 to the source of negative potential 22 in accordance with the above-described transistor action. The ow of collector current will cause the point 27 to rise to about minus 0.1 volt, which is positive relative to its potential whenl transistor 19 is oft Since the bistable device, or ilipop 28, can be switched lfrom one condition to the other only by a negative pulse, the relatively positive potential appearing at the point 27 has no effect on the status of ilip-op 28.

At sampling time, the negative gate pulse 18 is applied to the base of transistor 15 to forward bias the baseemitter junction, lturn the transistor on and give rise to transistor action thereat. There will be currentow from the ground reference potential 29 through the transistor 15, and through the resistor 24 to the source of plate, point 25,` at approximately a +6 volts potential above ground. With the point 25 at a positive potential above ground, the transistor 19 is biased olf and rendered non-conducting, causing the potential of point 27 to fall toward the minus 6 volt value of source 22. As long as the'transistor 19 does not conduct, the point 27 will be negative and the Hip-flop 28 will be transferred to the flop side 31, to either insure a reset of the flip-flop amasar .tential long enough to provide an output signal at 27 which approximates the input signal 18. This condition is not necessarily inherent in the system and is by design. As condensor 23 discharges, the point 25 will approach the -6 volt level of source 22, but as soon as the point 25 becomes more negative than ground, the transistor 19 will conduct and the point 27 will rise toward ground,

thereby terminating the output pulse. It, therefore, follows that the time duration of the output pulse is proportional to, but is not as long as, the R-C time constant of the resistor-capacitor circuitl 32 since the output pulse occurs only for the portion of time that the point 25 remains positive with respect to ground. Further examination of the circuit will reveal that the output pulse can be no longer than the length of the input pulse, sampling signal 18, because as soon as the transistor 15 is rendered non-conducting the point 25 will assume a -6 volt potential and the transistor 19 will be turned on.

If, after the sampling signal 18 has been applied to the system at the base of the transistor 15, the reject signal generator at 13 passes a positive reject pulse 17, a some-I what varied operation follows. The circuit operation as described in connection with the application of the pulse 18 will be similar up to a point. 'In response to pulse 18, transistor 15 is turned on, point 25 is raised abruptly to }-6 0 volts, and transistor 19 is turned 011. However, at time t1, in response to reject pulse 17, as shown in Fig. 2 by the dotted line superimposed over the signal generator pulse, the NPN transistor 33 will be rendered conducting due to the positive pulse applied to its base. With the transistor 33 conducting, the potential of point 34, previously held at 6.0 volts by diode 45 becomes relatively positive, i.e., rises from -6 volts toward ground,

thereby rendering the NPN transistor 35 conducting. As' soon as transistor 35 conducts, point'27 rises to almostVr zero or ground potential. It will be recalled from above that when transistor 15 is conducting, the condensor 23 discharges through transistor 15 and resistor 21, and that the R-C time constant was chosen to be long. When the transistor 35 conducts, a discharge path is provided for condensor 23 through transistor 15, transistor 35,I

resistor 26, to the negative potential source 22. Resistor 21 is chosen to be very much larger than resistor 26, and the low impedance path through the on transistor 35 which now shunts resistor 21 causes condensor 23 to discharge very rapidly, thereby causing the point 25 to approach rapidly a potential which is negative relative to ground. As soon as the potential at 25 becomes negative with respect to ground, the transistor 19 is again rendered conducting. The conduction of transistor `19 prevents point 27 from becoming appreciably negative, and there-l by continues the tiip-op 28 in the flip or reject state into which it was placed by reject pulse 17 as will be described below. The relationship between the output pulse without a reject pulse present, and the output with a reject pulse present, is shown in Fig. 2 by the waveforms 36 and 37.

Returning now to the instant at which the positive:

reject pulse 17 is applied to the base of the NPN transistor 33 and point 34 moves suddenly in a positive direction, it will be seen that this positive pulse on lead 38 is inverted in inverter 39 and passes as a negative pulse from the inverter 39 to flip-flop 28 causing the bistable device 28 to transfer to the llip side 40, which indicates that the comparison device output has been rejected.. It should be further understood that if the reject pulse; 17 ends before the input pulse 18 terminate's,`point 27' refbfb, been, that tbe reject pulse 17 becomes and, @Yen'tbbbsb tbeinput pulse .1,8 is still being applied, the reject Vpulse 17 will bfebt transfer of the hip-flop to the tlipf 4l), Moreover, even though the reject pulse 1 7 ends before input pulse litik does, the input pulse 18 isnot able to transfer the hip-dop baci; to the fl'opside $1. i i i* i l i Y i, In Fig. lfcoupled to the flip-flop 28, there is shown a lead' 41. When the'ilip-opnis themip state 401, the reject state,'a 'signal' is transmitted over lead 41j to the character recognitionsystem "171, which indicates,u to the system 11 that the document should "be Ncarried to the reject pocket. Y V Y Y l' l' The present inventive circuit has been described in operation with a character lrecognition system, with certain designated potential levels and with certain designated component values for purposes of illustration. It is to be clearlyunderstood lthat the component values and the designated potential levels could be altered depending upon the design requisites for any particular system without deviatingfrom the spirit and teaching of the present inventive circuit. WhileI have described my invention in connection with specific apparatus, this Hdescription is only by way of example, and not as a limitation to the scope of my invention as set forth in the objects thereof and in the accompanying claims. y

What I claim is: l. In a pulse generator circuit which provides an output signal in response. to an input signal, a control circuit to terminate said output signal irrespective of the presence ofV an application of said input signal, compris-V ing, a source` of input pulses, a controllable electron transferV device coupled to said source to be conditioned to conduct in response toa signal therefrom, a first voltage reference source, 'irst circuitry means coupling said controllable electron transfer device to saidV rst voltage reference source, a firstl electron flow path means, coupled to said rst voltage reference source, an electron storage. deYicCoupled betweenk said; electron transfer device and said first electron tio-yy path means, Saidl first electron flow path means in conjunction withy said" controllable electron transfer. device. providing a dischargepath forl said electron storage device, a second voltage reference source lcoupled to said electron. storage device to provide electron storage thereat-J output meansk coupled to said electron storage device to provide an output signal in tspnsb t a discharge thereof, Said Output Signal having av predetermined time duration directly proportionalto thedischargeztime of said, electron storagev device,l said electron.'stpragefdevice discharging Afor said` predetermined timel along said iirstl electrony ilowpathv in response tothe conduction of .said controllable electron transfer device, a controllable electron ow path meanscoupled to said electron storage deviccto be conditioned to, provide.l thereto. ay second discharge. path of conductivity to dischargejsaid electron storage device, in aI relatively short period of time when'compared to said predetermined time,

a' sourcefofcontrol signals coupled` to said controllable.

electronflow path means, said controllable electron. ow path. means conditioned,I inresponse toa control signal appliedy theretofto dischargey said electron; storage device-` p'riord to the,Vv endg of said predetermined time. thereby instar^1t`ane-fously terminating said outputl pulse.V irrespectiveofthe presence of saidinput pulse. j

` 2.1 ln'1 a'pulfse generatorc'v cuit which provides, an outl put'v'signal, in response. to,an` input signal, a control ciraccording toclfm, 1 whereinsaidxcontrollablel electron transfer device in udesahrst transistordevico.having its collector element coupled to said first .reference voltage source and wherein said controllable electron ow path means includes a second transistor device whose base element is coupled to said source of control signals and WhQSe collector element is coupled to said rst reference voltage sobres- 3. ln a pulse generator circuit which provides an output signal in response to an input signal, a control circuit according to claim l wherein said storage device and said first electron flow path means includes a series coupled resistor-capacitor. t

In a pulse generator circuit which provides an out put signal in response to an input signal, a control circuit according to Vclaim 1 wherein there is further included a bistable device having its first stable state input coupled to said output pulse and its second stable stateV input coupled to the input to said controllable electron ow path means to indicate when transferred to said first stable state that the output signal is acceptable and when transferred to said second stable state that the output signal is not acceptable.

5. In a pulse generator circuit which provides an output signal in response to an input signal, a control circuit according to claim l wherein the control signals are derived from the input pulse and are enveloped thereby.

6. In a pulsev generator circuit which provides an out| put signal in response to an input signal, a control, circuit to terminate said output signal irrespective of the presence of an application of said input signal, comprising a source of input signals, a rst transistor whose base elementis coupled to said source of input signals, a rst voltage reference source, rst circuitry means coupling the col'I lector element of said first transistor to said first voltage. reference source, a series connected.resistor-capacitor circuit coupled across said rst circuitry means, a second voltage reference source coupled to said capacitor to pro.- vide electron storage lthereat, output means coupled to said capacitonto provide an output signalin response to a discharge thereof, said output signal having a predetermined time durationv directly proportional tol the R-C time constant offsaid resistor-capacitor circuit, said capaciton discharging in responsel to the conduction of said' firsttransistor device, a secondk transistor device having its collector element coupled to said capacitor, and its emitter elementcoupled to said rst voltage reference source, a source of con-trol signals coupled to the base element of saidf second transistordevice, said second transistor device rendered conductingin responseto a control signal appliedtheretoto. suiciently discharge said capacitor substantial-v ly early with respect to the. time duration of saidl R-C"v time.4 constant thereby terminating saidI output p1.i1se, ir.v

respective ofthe presence. of an application ofsaid inputv pulse, and bistable indicating means coupled to` saidvoutput` signal and'snaidA second transistor base-,element to indicate respectively the-presence of,v an acceptable output` pulse in .onestate and a rejected output pulse in the other state thereof,

7. In a character recognition system wherein there is. a reading station to translate printed characters'into electrical signals and wherein there is provided a sampling signal when a printed character has been sufficiently translated into an` electrical signal` to provide a recognition thereof and areject signal when the reading station indicates substantially simultaneously al reading of more than one character, acontrol circuit -to operate` inresponse to said sampling signal and said reject signalV to provideV respectively an indication. of an acceptable or unacceptable character reading, comprising,Y a controllable electron; transfer device; coupled to said sampling signalto be conditioned to conduct thereby, aV first reference voltage source, rstl circuitry means coupling said controllable; electronA transfer device; to said first voltage reference sour-Q6; first electronV flow path means coupledV to said? fISt. ,Voltage reference Source, an velectron. Storagedevice- QQunled; between. Said.l electron.. transfer, device; andi said;

rst electron ow path means, said first electron flow path means in conjunction with said controllable electron transfer device providing a discharge path for said electron storage device, a second voltage reference source coupled to said electron storage device to provide electron storage thereat, output signal means coupled to said electron storage device to provide an output signal in response to a discharge thereof, said output signal having a predetermined time duration directly proportional to the discharge time of said electron storage device, said electron storage device discharging for said predetermined time along said first electron ilow path in response to the conduction of said controllable electron transfer device, a controllable electron flow path means coupled to said electron storage device to be conditioned to provide thereto a second electron ow path of high conductivity to discharge said electron storage circuitry in a relatively short period of time when compared to said predetermined time, said controllable electron ow path coupled to said reject signal to be conditioned in response thereto to discharge said electron storage device prior to the end of said predetermined time thereby instantaneously terminating said output signal, and a bistable device having its first state input coupled to said output signal and its second state input coupled to said reject signal to indicate in said rst state an acceptable character reading and in vsaid second state an unacceptable character reading.

No references cited 

